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1 215814f LTC2158-14 typical a pplica t ion fea t ures a pplica t ions descrip t ion dual 14-bit 310msps adc n communications n cellular basestations n software defined radios n medical imaging n high definition video n testing and measurement instruments n 68.8dbfs snr n 88db sfdr n low power: 724mw total n single 1.8v supply n ddr lvds outputs n easy-to-drive 1.32v p-p input range n 1.25ghz full power bandwidth s/h n optional clock duty cycle stabilizer n low power sleep and nap modes n serial spi port for configuration n pin-compatible 12-bit version n 64-lead (9mm 9mm) qfn package the lt c ? 2158-14 is a 2- channel simultaneous sampling 310msps 14- bit a/d converter designed for digitizing high frequency, wide dynamic range signals. it is perfect for demanding communications applications with ac per- formance that includes 68.8 db snr and 88 db spurious free dynamic range ( sfdr). the 1.25 ghz input bandwidth allows the adc to undersample high frequencies with good performance. the latency is only five clock cycles. dc specs include 1.2 lsb inl (typ), 0.35 lsb dnl (typ) and no missing codes over temperature. the transition noise is 2.11lsb rms . the digital outputs are double data rate (ddr) lvds. the enc + and enc C inputs can be driven differentially with a sine wave, pecl, lvds, ttl , or cmos inputs. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. s/h correction logic output drivers 14-bit pipelined adc core clock/duty cycle control da12_13 ? ? ? da0_1 db12_13 ? ? ? db0_1 clock analog input 215814 ta01 ddr lvds ddr lvds v dd ov dd ov dd ognd ognd gnd channel a s/h correction logic output drivers 14-bit pipelined adc core analog input channel b frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 ta01b 100 140120 ?20 LTC2158-14 32k point 2-tone fft , f in = 71mhz and 69mhz, 310msps www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 2 215814f a bsolu t e maxi m u m r a t ings supply voltage v dd , ov dd ................................................ C0. 3 v to 2v analog input voltage a ina /b + , a ina /b C , par / ser , sense ( note 3) ........................ C 0.3 v to (v dd + 0.2 v) digital input voltage enc + , enc C ( note 3) ................ C0. 3 v to (v dd + 0.3 v) cs , sdi , sck ( note 4) ........................... C 0.3 v to 3.9 v sdo ( note 4) ............................................. C 0.3 v to 3.9 v digital output voltage ................ C 0.3 v to ( ov dd + 0.3 v) operating temperature range ltc 2158 c ................................................ 0 c to 70 c ltc 2 158 i ............................................. C 40 c to 85 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) p in c on f igura t ion top view up package 64-lead (9mm 9mm) plastic qfn 65 gnd v dd 1 v dd 2 gnd 3 a ina + 4 a ina ? 5 gnd 6 sense 7 v ref 8 gnd 9 v cm 10 gnd 11 a inb ? 12 a inb + 13 gnd 14 v dd 15 v dd 16 48 ognd 47 da4_5 + 46 da4_5 ? 45 da2_3 + 44 da2_3 ? 43 da0_1 + 42 da0_1 ? 41 clkout + 40 clkout ? 39 db12_13 + 38 db12_13 ? 37 db10_11 + 36 db10_11 ? 35 db8_9 + 34 db8_9 ? 33 ognd 64 v dd 63 par/ser 62 cs 61 sck 60 sdi 59 sdo 58 gnd 57 da12_13 + 56 da12_13 ? 55 da10_11 + 54 da10_11 ? 53 da8_9 + 52 da8_9 ? 51 da6_7 + 50 da6_7 ? 49 ov dd v dd 17 gnd 18 enc + 19 enc ? 20 gnd 21 of ? 22 of + 23 db0_1 ? 24 db0_1 + 25 db2_3 ? 26 db2_3 + 27 db4_5 ? 28 db4_5 + 29 db6_7 ? 30 db6_7 + 31 ov dd 32 t jmax = 150c, ja = 27.4c/w exposed pad (pin 65) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2158cup-14#pbf ltc2158cup-14#trpbf ltc2158up-14 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2158iup-14#pbf ltc2158iup-14#trpbf ltc2158up-14 64-lead (9mm 9mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ www.datasheet.co.kr datasheet pdf - http://www..net/
3 215814f LTC2158-14 c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error differential analog input (note 6) l C7.5 1.2 7.5 lsb differential linearity error differential analog input l C1 0.35 1 lsb offset error (note 7) l C15 5 15 mv gain error internal reference external reference l C4.5 1.5 1 3 %fs %fs offset drift 20 v/c full-scale drift internal reference external reference 30 10 ppm/c ppm/c transition noise 2.11 lsb rms a nalog i npu t the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.74v < v dd < 1.9v l 1.32 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l v cm C 20mv v cm v cm + 20mv v v sense external voltage reference applied to sense external reference mode l 1.230 1.250 1.270 v i in1 analog input leakage current 0 < a in + , a in C < v dd , no encode l C1 1 a i in2 par /ser input leakage current 0 < par /ser < v dd l C1 1 a i in3 sense input leakage current 1.23v < sense < 1.27v l C1 1 a t ap sample-and-hold acquisition delay time 1 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 75 db bw-3b full-power bandwidth 1250 mhz dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions min typ max units snr signal-to-noise ratio 15mhz input 70mhz input 140mhz input l 66 68.8 68.4 67.7 dbfs dbfs dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 15mhz input 70mhz input 140mhz input l 70 88 85 79 dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 15mhz input 70mhz input 140mhz input l 80 98 95 90 dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 15mhz input 70mhz input 140mhz input l 65 68.7 68.4 67.2 dbfs dbfs dbfs crosstalk crosstalk between channels up to 315mhz input C95 db www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 4 215814f i n t ernal r e f erence c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.435 ? v dd C 18mv 0.435 ? v dd 0.435 ? v dd + 18mv v v cm output temperature drift 37 ppm/c v cm output resistance C1ma < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 30 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.74v < v dd < 1.9v 0.6 mv/v digi t al i npu t s a n d o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.5 v v r in input resistance (see figure 2) 10 k c in input capacitance (note 8) 2 pf digital inputs ( cs, sdi, sck) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 4 pf p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v dd analog supply voltage (note 9) l 1.74 1.8 1.9 v ov dd output supply voltage (note 9) l 1.74 1.8 1.9 v i vdd analog supply current l 355 395 ma i ovdd digital supply current 1.75ma lvds mode 3.5ma lvds mode l l 47 77 55 90 ma ma p diss power dissipation 1.75ma lvds mode 3.5ma lvds mode l l 724 777 810 873 mw mw p sleep sleep mode power clock disabled clocked at f s(max) <5 <5 mw mw p nap nap mode power clocked at f s(max) 202 mw www.datasheet.co.kr datasheet pdf - http://www..net/
5 215814f LTC2158-14 symbol parameter conditions min typ max units digital d ata outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 d igi t al inpu t s an d ou t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units f s sampling frequency (note 9) l 10 310 mhz t l enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 1.5 1.2 1.61 1.61 50 50 ns ns t h enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 1.5 1.2 1.61 1.61 50 50 ns ns digital d ata outputs t d enc to data delay c l = 5pf (note 8) l 1.7 2 2.3 ns t c enc to clkout delay c l = 5pf (note 8) l 1.3 1.6 2 ns t skew data to clkout skew t d C t c (note 8) l 0.3 0.4 0.55 ns pipeline latency 5 5 cycles spi port timing (note 8) t sck sck period write mode readback mode c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck set-up time l 5 ns t h sck to cs hold time l 5 ns t ds sdi set-up time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 310mhz, differential enc + /enc C = 2v p-p sine wave, input range = 1.32v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: recommended operating conditions. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 6 215814f typical p er f or m ance c harac t eris t ics LTC2158-14: integral nonlinearity (inl) LTC2158-14: differential nonlinearity (dnl) LTC2158-14: 32k point fft , f in = 15mhz, C1dbfs, 310msps LTC2158-14: 32k point fft , f in = 70mhz, C1dbfs, 310msps LTC2158-14: 32k point fft , f in = 150mhz, C1dbfs, 310msps LTC2158-14: 32k point fft , f in = 383mhz, C1dbfs, 310msps LTC2158-14: 32k point fft , f in = 421mhz, C1dbfs, 310msps LTC2158-14: 32k point fft , f in = 223mhz, C1dbfs, 310msps LTC2158-14: 32k point fft , f in = 185mhz, C1dbfs, 310msps output code 0 ?2.0 ?1.5 ?1.0 ?0.5 inl error (lsb) 0 0.5 2.0 1.5 1.0 4096 8192 12288 16383 215814 g01 output code 0 ?0.50 ?0.25 dnl error (lsb) 0 0.25 0.50 4095 8190 12285 16383 215814 g02 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g03 100 140120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g04 100 140120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g05 100 140120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g06 100 140120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g07 100 140120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g08 100 140120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g09 100 140120 ?20 www.datasheet.co.kr datasheet pdf - http://www..net/
7 215814f LTC2158-14 LTC2158-14: 32k point fft , f in = 907mhz, C1dbfs, 310msps LTC2158-14: 32k point 2-tone fft , f in = 71mhz and 69mhz, 310msps LTC2158-14: shorted input histogram LTC2158-14: sfdr vs input level, f in = 70mhz, 1.32v range, 310msps LTC2158-14: snr vs input level, f in = 70mhz, 1.32v range, 310msps LTC2158-14: 32k point fft , f in = 567mhz, C1dbfs, 310msps typical p er f or m ance c harac t eris t ics LTC2158-14: sfdr vs input frequency, C1dbfs, 1.32v range, 310msps LTC2158-14: snr vs input frequency, C1dbfs, 1.32v range, 310msps frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g10 100 140120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g11 100 140120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 g12 100 140120 ?20 output code 8192 0 count 10000 20000 8196 8200 8204 8208 8212 25000 5000 15000 8216 215814 g13 amplitude (dbfs) 0 sfdr (dbfs) 20 60 80 100 ?50 ?30 ?20 40 120 ?70 ?60 ?90 ?80 ?40 ?10 0 215814 g14 dbc dbfs amplitude (dbfs) 0 snr (dbfs) 10 30 40 50 ?50 ?30 ?20 20 70 60 ?60 ?40 ?10 0 215814 g15 dbc dbfs input frequency (mhz) 0 sfdr (dbfs) 40 90 200 400 600 20 70 30 80 10 0 60 50 100 300 800 1000 500 700 900 215814 g16 input frequency (mhz) 0 snr (dbfs) 60 75 200 400 600 50 55 45 40 70 65 100 300 800 1000 500 700 900 215814 g17 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 8 215814f typical p er f or m ance c harac t eris t ics LTC2158-14: frequency response LTC2158-14: i vdd vs sample rate, 15mhz sine wave input, C1dbfs sample rate (msps) 240 i vdd (ma) 280 300 320 62 186 248 260 360 340 0 124 310 215814 g19 1000 100 input frequency (mhz) input amplitude (dbfs) ?4.0 ?1.5 ?1.0 ?0.5 ?2.5 ?4.5 ?2.0 ?3.0 ?3.5 215814 g20 LTC2158-14: i ovdd vs sample rate, 15mhz sine wave input, C1dbfs sample rate (msps) i ovdd (ma) 40 50 60 50 150 200 250 30 80 70 0 100 300 215814 g18 lvds current 3.5ma lvds current 1.75ma p in func t ions v dd ( pins 1, 2, 15, 16, 17, 64): 1.8 v analog power supply . bypass to ground with 0.1 f ceramic capacitors. pins 1, 2, 64 can share a bypass capacitor. pins 15, 16, 17 can share a bypass capacitor. gnd (pins 3, 6, 9, 11, 14, 18, 21, 58, exposed pad pin 65): adc power ground. the exposed pad must be soldered to the pcb ground. a ina + ( pin 4): positive differential analog input for channel a. a ina C ( pin 5): negative differential analog input for channel a. sense (pin 7): reference programming pin. connecting sense to v dd selects the internal reference and a 0.66v input range. the same input voltage range can be achieved by applying an external 1.25v reference to sense. v ref (pin 8): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. nominally 1.25v. v cm ( pin 10): common mode bias output; nominally equal to 0.435 ? v dd . v cm should be used to bias the common mode of the analog inputs. bypass to ground with a 0.1f ceramic capacitor. a inb C (pin 12): negative differential analog input for channel b. a inb + ( pin 13): positive differential analog input for channel b. enc + (pin 19): encode input. conversion starts on the rising edge. enc C (pin 20): encode complement input. conversion starts on the falling edge. ognd (pins 33, 48): output driver ground. ov dd (pins 32, 49): 1.8 v output driver supply. bypass each pin to ground with separate 0.1 f ceramic capacitors. sdo (pin 59): serial interface data output. in serial pro- gramming mode, ( par / ser = 0v ), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open-drain n-channel mosfet output that requires an external 2 k pull-up resistor from 1.8v to 3.3 v. if readback from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. www.datasheet.co.kr datasheet pdf - http://www..net/
9 215814f LTC2158-14 sdi ( pin 60): serial interface data input. in serial program- ming mode , ( par / ser = 0 v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel pro- gramming mode ( par / ser = v dd ), sdi selects 3.5 ma or 1.75ma lvds output current ( see table 2). sdi can be driven with 1.8v to 3.3v logic. sck ( pin 61): serial interface clock input. in serial programming mode , ( par / ser = 0 v), sck is the serial interface clock input. in the parallel programming mode ( par / ser = v dd ), sck can be used to place the part in the low power sleep mode ( see table 2). sck can be driven with 1.8v to 3.3v logic. cs (pin 62): serial interface chip select input. in serial programming mode , ( par / ser = 0v), cs is the serial in- terface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode ( par / ser = v dd ), cs controls the clock duty cycle stabilizer ( see table 2). cs can be driven with 1.8v to 3.3v logic. par /ser (pin 63): programming mode selection pin. connect to ground to enable the serial programming mode where cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to en- able the parallel programming mode where cs , sck, sdi become parallel logic inputs that control a reduced set of the a/d operating modes. par / ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. lvds outputs the following pins are differential lvds outputs. the output current level is programmable. there is an optional internal 100? termination resistor between the pins of each lvds output pair. of C /of + (pins 22/23): over/underflow digital output. of + is high when an overflow or underflow has occurred. the overflows for channel a and channel b are multiplexed together. d b0_1 C /d b0_1 + to d b12_13 C /d b12_13 + (pins 24/25, 26/27, 28/29, 30/31, 34/35, 36/37, 38/39): channel b double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (db0, db2, db4, db6, db8, db10, db12) appear when clkout + is low. the odd data bits ( db1, db3, db5, db7, db9, db11, db13) appear when clkout + is high. clkout C /clkout + (pins 40/41): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. d a0_1 C /d a0_1 + to d a12_13 C /d a12_13 + (pins 42/43, 44/45, 46/47, 50/51, 52/53, 54/55, 56/57): channel a double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (da0, da2, da4, da6, da8, da10, da12) appear when clkout + is low. the odd data bits ( da1, da3, da5, da7, da9, da11, da13) appear when clkout + is high. p in func t ions www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 10 215814f func t ional b lock diagra m figure 1. functional block diagram s/h v cm buffer buffer buffer gnd v cm 0.1f correction logic output drivers 14-bit pipelined adc core clock/duty cycle control 1.25v reference range select clock analog input 215814 f01 ddr lvds ddr lvds v dd ov dd ognd cs channel a channel b gnd s/h correction logic output drivers spi 14-bit pipelined adc core analog input ov dd ognd v ref 2.2f gnd sense sck sdi par/ ser da12_13 ? ? ? da0_1 db12_13 ? ? ? db0_1 www.datasheet.co.kr datasheet pdf - http://www..net/
11 215814f LTC2158-14 ti m ing diagra m s double data rate output timing, all outputs are differential lvds t h t c t d t l of_a n-5 of_b n-5 of_a n-4 of_b n-4 of_a n-3 of_b n-3 t skew da0 n-5 da1 n-5 da0 n-4 da1 n-4 da0 n-3 da1 n-3 da12 n-5 da13 n-5 da12 n-4 da13 n-4 da12 n-3 da13 n-3 db0 n-5 db1 n-5 db0 n-4 db1 n-4 db0 n-3 db1 n-3 db12 n-5 db13 n-5 db12 n-4 db13 n-4 db12 n-3 db13 n-3 t ap n + 1 n + 2 n + 3 n enc ? enc + db0_1 + db0_1 ? da0_1 + da0_1 ? db12_13 + db12_13 ? da12_13 + da12_13 ? clkout + clkout ? of + of ? 215814 td01 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 12 215814f t i m ing d iagra m s a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 2158 td02 cs sck sdi r/w sdo high impedance www.datasheet.co.kr datasheet pdf - http://www..net/
13 215814f LTC2158-14 converter operation the LTC2158-14 is a two- channel, 14-bit 310msps a/d converter powered by a single 1.8 v supply. the analog inputs must be driven differentially. the en- code inputs should be driven differentially for optimal performance. the digital outputs are double data rate lvds. additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and- hold circuits (figure 2). the inputs must be driven differ- entially around a common mode voltage set by the v cm output pin, which is nominally 0.435 ? v dd . for the 1.32 v input range, the inputs should swing from v cm C 0.33 v to v cm + 0.33 v. there should be 180 phase difference between the inputs. the two channels are simultaneously sampled by a shared encode circuit. input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample- and- hold switching, and also limits wide band noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc compo- nent values should be chosen based on the applications specific input frequency. transformer-coupled circuits figure 3 shows the analog input being driven by an rf transformer with the common mode supplied through a pair of resistors via the v cm pin. at higher input frequencies a transmission line balun transformer (figures 4 and 5) has better balance, resulting in lower a/d distortion. 2pf r on 20 r on 20 v dd v dd LTC2158-14 a in + 215814 f02 2pf v dd a in ? enc ? enc + 2pf 2pf 1.2v 10k 25 25 4.7 4.7 10 0.1f 10pf 0.1f LTC2158-14 in 0.1f t1: macom etc1-1t 215814 f03 a in + a in ? v cm figure 2. equivalent input circuit. only one of two analog channels is shown figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz a pplica t ions i n f or m a t ion figure 4. recommended front-end circuit for input frequencies from 15mhz to 150mhz 45 45 10 4.7 4.7 0.1f 0.1f 100 in 0.1f 0.1f t1: maba 007159-000000 t2: wbc1-1l 215814 f04 LTC2158-14 a in + a in ? v cm www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 14 215814f a pplica t ions i n f or m a t ion figure 5. recommended front-end circuit for input frequencies from 150mhz to 900mhz figure 6. front-end circuit using a high speed differential amplifier amplifier circuits figure 6 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figures 3 and 5) should convert the signal to differential before driving the a/d. the a/d cannot be driven single-ended. reference the LTC2158-14 has an internal 1.25 v voltage reference. for a 1.32 v input range with internal reference, connect sense to v dd . for a 1.32 v input range with an external reference, apply a 1.25 v reference voltage to sense (figure 7). encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. the encode inputs are internally biased to 1.2 v through 10k equivalent resistance (figure 8). if the common mode of the driver is within 1.1 v to 1.5 v, it is possible to drive the encode inputs directly. otherwise a transformer or coupling capacitors are needed ( figures 9 and 10). the maximum ( peak) voltage of the input signal should never exceed v dd +0.1v or go below C0.1v. 4.7 4.7 50 50 0.1f a in + a in ? 0.1f 3pf 3pf 3pf v cm LTC2158-14 215814 f06 input 0.1f 45 45 10 100 4.7 4.7 0.1f 0.1f in 0.1f 0.1f t1: maba 007159-000000 215814 f05 LTC2158-14 a in + a in ? v cm figure 7. reference circuit figure 8. equivalent encode input circuit v dd LTC2158-14 215814 f08 1.2v 10k enc + enc ? scaler/ buffer v ref 2.2f sense 1.25v LTC2158-14 215814 f07 5 adc reference sense detector www.datasheet.co.kr datasheet pdf - http://www..net/
15 215814f LTC2158-14 a pplica t ions i n f or m a t ion clock duty cycle stabilizer for good performance the encode signal should have a 50% (5%) duty cycle. if the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. the duty cycle stabilizer is enabled via spi register a 2 ( see table 3) or by cs in parallel programming mode. for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. in this case, care should be taken to make the clock a 50% (5%) duty cycle. digital outputs the digital outputs are double data rate lvds signals. two data bits are multiplexed and output on each differential figure 9. sinusoidal encode drive output pair. there are seven lvds output pairs for channel a (da0_1 + /da0_1 C through da12_13 C /da12_13 + ) and seven pairs for channel b ( db0_1 + / db0_1 C through db12_13 C /db12_13 + ). overflow (of + /of C ) and the data output clock (clkout + /clkout C ) each have an lvds output pair. note that overflow for both channels is mul- tiplexed onto the of + /of C output pair. by default the outputs are standard lvds levels : 3.5 ma output current and a 1.25 v output common mode volt- age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. LTC2158-14 v dd 215814 f09 1.2v 10k 50 100 50 0.1f 0.1f t1: macom etc1-1-13 figure 10. pecl or lvds encode drive v dd LTC2158-14 pecl or lvds input 215814 f10 1.2v 10k 100 0.1f 0.1f enc + enc ? www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 16 215814f a pplica t ions i n f or m a t ion programmable lvds output current the default output driver current is 3.5 ma. this current can be adjusted by serially programming mode control register a 3 ( see table 3). available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. optional lvds driver internal termination in most cases, using just an external 100? termination resistor will give excellent lvds signal integrity. in addi- tion, an optional internal 100? termination resistor can be enabled by serially programming mode control register a3. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. overflow bit the overflow output bit ( of) outputs a logic high when the analog input is either overranged or underranged. the overflow bit has the same pipeline latency as the data bits. the of output is double data rate; when clkout + is low, channel as overflow is available; when clkout + is high, channel bs overflow is available. phase shifting the output clock to allow adequate set-up and hold time when latching the output data, the clkout + signal may need to be phase shifted relative to the data output bits. most fpgas have this feature; this is generally the best place to adjust the timing. alternatively, the adc can also phase shift the clkout + / clkout C signals by serially programming mode control register a2. the output clock can be shifted by 0, 45, 90, or 135. to use the phase shifting feature the clock duty cycle stabilizer must be turned on. another con- trol register bit can invert the polarity of clkout + and clkout C , independently of the phase shift. the combina- tion of these two features enables phase shifts of 45 up to 315 (figure 11). figure 11. phase shifting clkout clkout + d0-d13, of phase shift 0 45 90 135 180 225 270 315 clkinv 0 0 0 0 1 1 1 1 clkphase1 mode control bits 0 0 1 1 0 0 1 1 clkphase0 0 1 0 1 0 1 0 1 215814 f11 enc + www.datasheet.co.kr datasheet pdf - http://www..net/
17 215814f LTC2158-14 figure 12. functional equivalent of digital output randomizer figure 13. decoding a randomized digital output signal a pplica t ions i n f or m a t ion d ata format table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. by default the output data format is offset binary. the 2 s complement format can be selected by serially program- ming mode control register a4. table 1. output codes vs input voltage a in + C a in C (1.32v range) of d13-d0 (offset binary) d13-d0 (2s complement) >0.66v +0.66v +0.6599194v 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.0000806v +0.000000v C0.0000806v C0.0001611v 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C0.6599194v C0.66v < C0.66v 0 0 1 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000 digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclu- sive - or logic operation between the lsb and all other data output bits. to decode, the reverse operation is appliedan exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout out- puts are not affected. the output randomizer is enabled by serially programming mode control register a4. clkout clkout of d13/d0 d12/d0 ? ? ? d1/d0 d0 215814 f12 of d13 d12 d1 d0 randomizer on d13 fpga pc board d12 ? ? ? d1 d0 215814 f13 d0 d1/d0 d12/d0 d13/d0 of clkout LTC2158-14 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 18 215814f alternate bit polarity another feature that may reduce digital feedback on the circuit board is the alternate bit polarity mode. when this mode is enabled, all of the odd bits ( d1, d3, d5, d7, d9, d11, d13) are inverted before the output buffers. the even bits ( d0, d2, d4, d6, d8, d10, d12), of and clkout are not affected. this can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. the digital output is decoded at the receiver by inverting the odd bits ( d1, d3, d5, d7, d9, d11, d13.) the alternate bit polarity mode is independent of the digital output ran- domizereither both or neither function can be on at the same time. the alternate bit polarity mode is enabled by serially programming mode control register a4. digital output test patterns to allow in-circuit testing of the digital interface to the a/d, there are several test modes that force the a/d data outputs (of, d13 to d0) to known values: all 1s: all outputs are 1 all 0s: all outputs are 0 alternating: outputs change from all 1 s to all 0 s on alternating samples checkerboard: outputs change from 101010101010101 to 010101010101010 on alternating samples. the digital output test patterns are enabled by serially programming mode control register a4. when enabled, the test patterns override all other formatting modes: 2s complement, randomizer, alternate-bit polarity. output disable the digital outputs may be disabled by serially program- ming mode control register a3. all digital outputs includ- ing of and clkout are disabled. the high impedance disabled state is intended for long periods of inactivity, it is not designed for multiplexing the data bus between multiple converters. sleep mode the a/d may be placed in sleep mode to conserve power. in sleep mode the entire a/d converter is powered down, resulting in < 5 mw power consumption. if the encode input signal is not disabled the power consumption will be higher ( up to 5 mw at 310 msps). sleep mode is enabled by mode control register a 1 ( serial programming mode), or by sck (parallel programming mode). in the serial programming mode it is also possible to dis- able channel b while leaving channel a in normal operation. the amount of time required to recover from sleep mode depends on the size of the bypass capacitor on v ref . for the suggested value in figure 1, the a /d will stabilize after 0.1ms + 2500 ? t p where t p is the period of the sampling clock. nap mode in nap mode the a/d core is powered down while the internal reference circuits stay active, allowing faster wake-up. recovering from nap mode requires at least 100 clock cycles. nap mode is enabled by power-down register a1 in the serial programming mode. wake-up time from nap mode is guaranteed only if the clock is kept running, otherwise sleep mode wake-up conditions apply. device programming modes the operating modes of the LTC2158-14 can be pro- grammed by either a parallel interface or a simple serial interface. the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par / ser should be tied to v dd . the cs , sck and sdi pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5 v, or 3.3v cmos logic. table 2 shows the modes set by cs , sck and sdi. a pplica t ions i n f or m a t ion www.datasheet.co.kr datasheet pdf - http://www..net/
19 215814f LTC2158-14 table 2. parallel programming mode control bits ( par / ser = v dd ) pin description cs clock duty cycle stabilizer control bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on sck power down control bit 0 = normal operation 1 = sleep mode (entire adc is powered down) sdi lvds current selection bit 0 = 3.5ma l vds current mode 1 = 1.75ma l vds current mode serial programming mode to use the serial programming mode, par / ser should be tied to ground. the cs , sck, sdi and sdo pins become a serial interface that program the a/d control registers. data is written to a register with a 16- bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first sixteen rising edges of sck. any sck rising edges after the first sixteen are ignored. the data transfer ends when cs is taken high again. the first bit of the 16- bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data (d 7:d0) will be writ- ten to the register set by the address bits ( a6:a0). if the r/w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin ( see the timing diagrams). during a readback command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and readback is not needed, then sdo can be left floating and no pull-up resistor is needed. table 3 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset it is neces- sary to write 1 in register a 0 ( bit d7). after the reset is complete, bit d7 is automatically set back to zero. this register is write-only. grounding and byp assing the LTC2158-14 requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the adc. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref pins. bypass capacitors must be located as close to the pins as possible. size 0402 ceramic capacitors are recommended. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the LTC2158-14 is trans- ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance , the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias. a pplica t ions i n f or m a t ion www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 20 215814f a pplica t ions i n f or m a t ion table 3. serial programming mode register map ( par /ser = gnd). x indicates an unused bit that is read back as 0 register a0: reset register (address 00h) write only d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = reset disabled 1 = software reset. all mode control registers are reset to 00h. this bit is automatically set back to zero after the reset is complete. bits 6-0 unused bits register a1: power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x sleep nap pdb 0 bits 7-4 unused bit bit 3 sleep 0 = normal operation 1 = power down entire adc bit 2 nap 0 = normal mode 1 = low power mode for both channels bit 1 pdb 0 = normal operation 1 = power down channel b. channel a operates normally. bit 0 must be set to 0 register a2: timing register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x clkinv clkphase1 clkphase0 dcs bits 7-4 unused bit bit 3 clkinv output clock invert bit 0 = normal clkout polarity (as shown in the timing diagrams) 1 = inverted clkout polarity bits 2-1 clkphase1:clkphase0 output clock phase delay bits 00 = no clkout delay (as shown in the timing diagrams) 01 = clkout + /clkout C delayed by 45 (clock period ? 1/8) 10 = clkout + /clkout C delayed by 90 (clock period ? 1/4) 11 = clkout + /clkout C delayed by 135 (clock period ? 3/8) note: if the clkout phase delay feature is used, the clock duty cycle stabilizer must also be turned on. bit 0 dcs clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on www.datasheet.co.kr datasheet pdf - http://www..net/
21 215814f LTC2158-14 register a3: output mode register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 x x x ilvds2 ilvds1 ilvds0 termon outoff bits 7-5 unused bit bits 4-2 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 1 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2 the current set by ilvds2:ilvds0 bit 0 outoff digital output mode control bits 0 = digital outputs are enabled 1 = digital outputs are disabled (high impedance) register a4: d ata format register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 outtest2 outtest1 outtest0 abp 0 dteston rand twoscomp bits 7-5 outtest2:outtest0 digital output test pattern bits 000 = all digital outputs = 0 001 = all digital outputs = 1 010 = alternating output pattern. of, d13-d0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111 100 = checkerboard output pattern. of, d13-d0 alternate between 101 0101 0101 0101 and 010 1010 1010 1010 note 1: other bit combinations are not used. note 2: patterns from channel a and channel b may not be synchronous. bit 4 abp alternate bit polarity mode control bit 0 = alternate bit polarity mode off 1 = alternate bit polarity mode on bit 3 must be set to 0 bit 2 dteston enable the digital output test patterns (set by bits 7-5) 0 = normal mode 1 = enable the digital output t est patterns bit 1 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 0 twoscomp tw o s complement mode control bit 0 = offset binary data format 1 = tw o s complement data format a pplica t ions i n f or m a t ion www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 22 215814f typical a pplica t ions silkscreen top top side www.datasheet.co.kr datasheet pdf - http://www..net/
23 215814f LTC2158-14 t ypical applica t ions inner layer 2 gnd inner layer 3 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 24 215814f t ypical applica t ions inner layer 4 inner layer 5 www.datasheet.co.kr datasheet pdf - http://www..net/
25 215814f LTC2158-14 t ypical applica t ions bottom side www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 26 215814f t ypical applica t ions LTC2158-14 schematic par/ser spi bus encode clock digital outputs r33 LTC2158-14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd v dd gnd a ina + a ina ? gnd sense v ref gnd v cm gnd a inb ? a inb + gnd v dd v dd v dd v dd ov dd c13, 0.1f 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v dd par/ser cs sck sdi sdo gnd da12_ 13 + da12_ 13 ? da1 0_ 11 + da1 0_ 11 ? da8_9 + da8_9 ? da6_7 + da6_7 ? ov dd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v dd gnd enc + enc ? gnd of ? of + db0_1 ? db0_1 + db2_3 ? db2_3 + db4_5 ? db4_5 + db6_7 ? db6_7 + ov dd 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ognd da4_5 + da4_5 ? da2_3 + da2_3 ? da0_1 + da0_1 ? clkout + clkout ? db12_13 + db12_13 ? db10_11 + db10_11 ? db8_9 + db8_9 ? ognd ov dd r34 a ina ? sense a ina + c4 2.2f c12 0.1f c14 0.1f r8 c29, 0.1f r6 r7 a inb ? a inb + c7 0.1f c78 0.1f c79 0.1f r56 215814 ta09 r12 www.datasheet.co.kr datasheet pdf - http://www..net/
27 215814f LTC2158-14 p ackage descrip t ion information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705 rev c) 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 6463 1 2 bottom view?exposed pad 7.15 0.10 7.15 0.10 7.50 ref (4-sides) 0.75 0.05 r = 0.10 typ r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (up64) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 7.50 ref (4 sides) 7.15 0.05 7.15 0.05 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer c = 0.35 please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC2158-14 28 215814f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 1011 ? printed in usa r ela t e d p ar t s s/h correction logic output drivers 14-bit pipelined adc core clock/duty cycle control da12_13 ? ? ? da0_1 db12_13 ? ? ? db0_1 clock analog input 215814 ta10a ddr lvds ddr lvds v dd ov dd ov dd ognd gnd channel a s/h correction logic output drivers 14-bit pipelined adc core analog input ognd channel b frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215814 ta10b 100 140120 ?20 LTC2158-14: 32k point 2-tone fft , f in = 71mhz and 69mhz, 310msps typical a pplica t ion part number description comments adcs ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 77.7db snr, 100db sfdr, 64-lead qfn package ltc2157-14/ ltc2156-14/ ltc2155-14 14-bit, 250msps/210msps/170msps, 1.8v dual adc, ddr lvds outputs 650mw/616mw/567mw, 70db snr, 90db sfdr, 64-lead qfn package ltc2157-12/ ltc2156-12/ ltc2155-12 12-bit, 250msps/210msps/170msps, 1.8v dual adc, ddr lvds outputs 588mw/543mw/495mw, 68.5db snr, 90db sfdr, 64-lead qfn package ltc2242-12/ltc2241-12/ ltc2240-12 12-bit, 250msps/210msps/170msps, 2.5v adc, lvds outputs 740mw/585mw/445mw, 65.5db snr, 80db sfdr, 64-lead qfn package ltc2262-14 14-bit, 150msps 1.8v adc, ultralow power 149mw, 72.8db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 40-lead qfn package rf mixers/demodulators lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 3.5ghz, nf = 12.5db, 50 single-ended rf and lo ports lt5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifiers/filters ltc6409 10ghz gbw, 1.1nv/hz differential amplifier/ adc driver 88db sfdr at 100mhz, input range includes ground 52 ma supply current , 3mm 2mm qfn package ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 package ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1nv/hz total input noise, 80ma supply current per amplifier, 3mm 4mm qfn-20 package receiver subsystems ltm9002 14-bit dual channel if/baseband receiver subsystem integrated dual high speed adc, passive filters and fixed gain differential amplifiers ltm9003 12-bit digital predistortion receiver integrated 12-bit 250msps adc, down-converting mixer with 0.4ghz to 3.8ghz input frequency range, 125mhz bandpass filter www.datasheet.co.kr datasheet pdf - http://www..net/

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